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TDA9981B
HDMI transmitter up to 150 MHz pixel rate with 3 x 8-bit video inputs and 4 x I2S-bus with S/PDIF
Rev. 01 -- 4 July 2008 Product data sheet
1. General description
The TDA9981B is an HDMI transmitter (which also supports DVI) that enables a 3 x 8-bit RGB or YCbCr video stream (with a pixel rate up to 150 MHz for the TDA9981BHL/15 version), up to 4 I2S-bus audio streams (with an audio sampling rate up to 192 kHz) and the additional information required by all the HDMI 1.2a standards. In order to be compatible with most applications, the TDA9981B integrates a full programmable input formatter and color space conversion block. The video input formats accepted are YCbCr 4 : 4 : 4 (up to 3 x 8-bit), YCbCr 4 : 2 : 2 semi-planar (up to 2 x 12-bit), YCbCr 4 : 2 : 2 compliant with ITU656 and ITU656-like (up to 1 x 12-bit). For ITU656-like formats, double edges are supported so that data can be sampled on rising and falling edges. The device can be controlled via an I2C-bus interface.
2. Features
I 3 x 8-bit video data input bus, CMOS and LV-TTL compatible I Horizontal synchronization, vertical synchronization and Data Enable (DE) inputs or VREF, HREF and FREF could be used for input data synchronization I Pixel rate clock input can be made active on one or both edges (selectable by I2C-bus) I The TDA9981B has 4 I2S-bus audio input channels and 1 S/PDIF channel; audio sampling rate up to 192 kHz I 250 MHz to 1.50 GHz HDMI transmitter operation I Programmable input formatter and upsampler/interpolator allows input of any of the 4 : 4 : 4, 4 : 2 : 2 semi-planar, 4 : 2 : 2 ITU656 and ITU656-like formats I Programmable color space converter: N RGB to YCbCr N YCbCr to RGB I Controllable via I2C-bus I Low power dissipation I 1.8 V and 3.3 V power supplies I Power-down mode I Hard reset
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
3. Applications
I I I I I I I I I DVD players and recorders Set-Top Box (STB) AV receivers and amplifiers (repeater) Camcorders Digital still cameras Media players PVRs Media centers PCs, graphics add-in boards, notebook PCs Switches
4. Quick reference data
Table 1. Quick reference data VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 C to 85 C. Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 C; unless otherwise specified. Symbol VDDA(FRO_3V3) VDDA(PLL_3V3) VDDD(3V3) VDDH(3V3) VDDC(1V8) Tamb fclk(max) Pcons Ptot Ppd Parameter free running oscillator 3.3 V analog supply voltage PLL 3.3 V analog supply voltage digital supply voltage (3.3 V) HDMI supply voltage (3.3 V) core supply voltage (1.8 V) ambient temperature maximum clock frequency power consumption total power dissipation power dissipation in Power-down mode maximum clock frequency power consumption total power dissipation power dissipation in Power-down mode
[2] [2] [2] [1] [1] [1]
Conditions
Min 3.0 3.0 3.0 3.0 1.65 0 81 -
Typ 3.3 3.3 3.3 3.3 1.8 235 369 14
Max 3.6 3.6 3.6 3.6 1.95 85 288 438 19
Unit V V V V V C MHz mW mW mW
TDA9981BHL/8 and TDA9981BHL/15
TDA9981BHL/8; up to 81 MHz
TDA9981BHL/15; up to 150 MHz fclk(max) Pcons Ptot Ppd
[1] [2]
150 -
-
-
MHz mW mW mW
381.5 468 515.5 618 14 19
Worst case: video input format: 720p at 60 Hz (RGB 4 : 4 : 4 embedded sync), video output format: 720p at 60 Hz (YCbCr 4 : 4 : 4). Video input format: 1080p (RGB 4 : 4 : 4 embedded sync, rising edge), video output format: 1080p (RGB 4 : 4 : 4).
TDA9981B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 4 July 2008
2 of 41
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
5. Ordering information
Table 2. Ordering information Package Name TDA9981BHL LQFP80 Description plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm Version SOT315-1 Type number
5.1 Ordering options
Table 3. Survey of type numbers Sampling frequency (MHz) 81 150 Application customer specific version customer specific version Extended type number TDA9981BHL/8/C1xx TDA9981BHL/15/C1xx
TDA9981B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 4 July 2008
3 of 41
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Product data sheet Rev. 01 -- 4 July 2008
(c) NXP B.V. 2008. All rights reserved. TDA9981B_1
6. Block diagram
NXP Semiconductors
VPP RST_N 42 3
VDDC(1V8) VDDD(3V3)
VDDH(3V3) VDDA(PLL_3V3) 28, 34 38 I2C_SCL 43 I2C_SDA 44 A0 41 A1 40 20 DDC_SCL DDC_SDA
VDDA(FRO_3V3)
13, 48, 16, 45, 23 71 59, 74
HPD
18
HPD MANAGEMENT
HARD RESET
I2C-BUS SLAVE
DDC-BUS
19
AP7 to AP0 ACLK
4 to 11 12 AUDIO PROCESSING YCbCr DATA ISLAND PACKET IRQ GENERATION
17
INT
INFORMATION FRAMES AND PACKETS 68 to 70, 75 to 79 57 and 58, 61 to 65, 67 49 to 56 2 1 80 66 VIDEO INPUT PROCESSOR
27 26 30 VIDEO PROCESSING RGB YCbCr 4 : 4 : 4 3 x 8-bit UPSAMPLING FROM 4:2:2 TO 4 : 4 : 4(1) COLOR SPACE CONVERTER RGB TO YUV YUV TO RGB (4 : 4 : 4)(1) DOWNSAMPLING FROM 4:4:4 TO 4 : 2 : 2(1) HDMI SERIALIZER 29 33 32 36 35
TXC+ TXC- TX0+ TX0- TX1+ TX1- TX2+ TX2-
VPA[7:0]
VPB[7:0] VPC[7:0] VSYNC/VREF HSYNC/HREF DE/FREF VCLK
YCbCr 4 : 2 : 2 ITU656 or ITU656-like 14, 47, 72 VSSD
2 x 12-bit or 1 x 12-bit 15, 60, 73 VSSC 25, 31, 37 VSSH
TDA9981B
150 MHz pixel rate HDMI transmitter
22 VSSA(FRO_3V3)
39 VSSA(PLL_3V3)
46 VSSA(PLL_1V8)
21 TM
24 EXT_SWING
001aai221
TDA9981B
(1) Block can be bypassed.
4 of 41
Fig 1.
Block diagram
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
7. Pinning information
7.1 Pinning
71 VDDD(3V3) 80 DE/FREF 74 VDD(1V8)
69 VPA[6]
68 VPA[7]
65 VPB[1]
79 VPA[0]
78 VPA[1]
77 VPA[2]
76 VPA[3]
75 VPA[4]
70 VPA[5]
67 VPB[0]
64 VPB[2]
63 VPB[3]
62 VPB[4]
HSYNC/HREF VSYNC/VREF VPP AP7 AP6 AP5 AP4 AP3 AP2
1 2 3 4 5 6 7 8 9
61 VPB[5]
66 VCLK
73 VSSC
72 VSSD
60 VSSC 59 VDDC(1V8) 58 VPB[6] 57 VPB[7] 56 VPC[0] 55 VPC[1] 54 VPC[2] 53 VPC[3] 52 VPC[4] 51 VPC[5] 50 VPC[6] 49 VPC[7] 48 VDDD(3V3) 47 VSSD 46 VSSA(PLL_1V8) 45 VDDC(1V8) 44 I2C_SDA 43 I2C_SCL 42 RST_N 41 A0
AP1 10 AP0 11 ACLK 12 VDDD(3V3) 13 VSSD 14 VSSC 15 VDDC(1V8) 16 INT 17 HPD 18 DDC_SDA 19 DDC_SCL 20
TDA9981B
TM 21
VSSA(FRO_3V3) 22
VDDA(FRO_3V3) 23
EXT_SWING 24
VSSH 25
TXC- 26
TXC+ 27
VDDH(3V3) 28
TX0- 29
TX0+ 30
VSSH 31
TX1- 32
TX1+ 33
VDDH(3V3) 34
TX2- 35
TX2+ 36
VSSH 37
VDDA(PLL_3V3) 38
VSSA(PLL_3V3) 39
A1 40
001aai219
Fig 2.
Pin configuration
7.2 Pin description
Table 4. Symbol Pin description Pin Type[1] Description I I P I I I horizontal synchronization or reference input vertical synchronization or reference input programming voltage if OTP memory is available (must always be connected to the ground of the digital core in normal operation) audio port 7 input; auxiliary (AUX) audio port 6 input; S/PDIF stream audio port 5 input; optional master clock MCLK for S/PDIF
(c) NXP B.V. 2008. All rights reserved.
HSYNC/HREF 1 VSYNC/VREF 2 VPP AP7 AP6 AP5
TDA9981B_1
3 4 5 6
Product data sheet
Rev. 01 -- 4 July 2008
5 of 41
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
Pin description ...continued Pin Type[1] Description 7 8 9 10 11 12 13 14 15 16 17 I I I I I I P G G P O audio port 4 input; I2S-bus port 3 audio port 3 input; I2S-bus port 2 audio port 2 input; I2S-bus port 1 audio port 1 input; I2S-bus port 0 audio port 0 input; word select WS for I2S-bus audio clock input; clock SCK for I2S-bus supply voltage for input ports (3.3 V) ground for input ports ground for digital core supply voltage for digital core (1.8 V) interrupt output (open drain); warns the external microprocessor that a special event has occurred; must be connected to a pull-up resistor; 5 V tolerant hot plug detect input; 5 V tolerant DDC-bus data input/output (open drain); must be connected to a pull-up resistor; 5 V tolerant DDC-bus clock output (open drain); must be connected to a pull-up resistor; 5 V tolerant internal test mode input (must be connected to the ground of the digital core in normal operation) analog ground for free running oscillator analog supply voltage for free running oscillator (3.3 V) external swing adjust input; a fixed resistor must be connected between this pin and pin VDDH(3V3) to set the HDMI output swing (see Section 8.14.1) ground for HDMI transmitter negative clock channel for HDMI output positive clock channel for HDMI output supply voltage for HDMI transmitter (3.3 V) negative data channel 0 for HDMI output positive data channel 0 for HDMI output ground for HDMI transmitter negative data channel 1 for HDMI output positive data channel 1 for HDMI output supply voltage for HDMI transmitter (3.3 V) negative data channel 2 for HDMI output positive data channel 2 for HDMI output ground for HDMI transmitter analog supply voltage for PLL (3.3 V) analog ground reference for PLL I2C-bus slave address input 1; bit 1 I2C-bus slave address input 0; bit 0 hard reset input; active LOW
(c) NXP B.V. 2008. All rights reserved.
Table 4. Symbol AP4 AP3 AP2 AP1 AP0 ACLK VDDD(3V3) VSSD VSSC VDDC(1V8) INT
HPD DDC_SDA DDC_SCL TM VSSA(FRO_3V3) VDDA(FRO_3V3) EXT_SWING
18 19 20 21 22 23 24
I I/O O I G P I
VSSH TXC- TXC+ VDDH(3V3) TX0- TX0+ VSSH TX1- TX1+ VDDH(3V3) TX2- TX2+ VSSH VDDA(PLL_3V3) VSSA(PLL_3V3) A1 A0 RST_N
TDA9981B_1
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
G O O P O O G O O P O O G P G I I I
Product data sheet
Rev. 01 -- 4 July 2008
6 of 41
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
Pin description ...continued Pin Type[1] Description 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 I I/O P G G P I I I I I I I I I I P G I I I I I I I I I I P G G P I I I I I I I2C-bus clock input of device (open drain); must be connected to a pull-up resistor; 5 V tolerant I2C-bus data input/output of device (open drain); must be connected to a pull-up resistor; 5 V tolerant supply voltage for digital core (1.8 V) analog ground reference for PLL ground for input ports supply voltage for input ports (3.3 V) video port C input bit 7 video port C input bit 6 video port C input bit 5 video port C input bit 4 video port C input bit 3 video port C input bit 2 video port C input bit 1 video port C input bit 0 video port B input bit 7 video port B input bit 6 supply voltage for digital core (1.8 V) ground for digital core video port B input bit 5 video port B input bit 4 video port B input bit 3 video port B input bit 2 video port B input bit 1 video pixel clock input video port B input bit 0 video port A input bit 7 video port A input bit 6 video port A input bit 5 supply voltage for input ports (3.3 V) ground for input ports ground for digital core supply voltage for digital core (1.8 V) video port A input bit 4 video port A input bit 3 video port A input bit 2 video port A input bit 1 video port A input bit 0 video data enable input or field reference input
Table 4. Symbol I2C_SCL I2C_SDA VDDC(1V8)
VSSA(PLL_1V8) VSSD VDDD(3V3) VPC[7] VPC[6] VPC[5] VPC[4] VPC[3] VPC[2] VPC[1] VPC[0] VPB[7] VPB[6] VDDC(1V8) VSSC VPB[5] VPB[4] VPB[3] VPB[2] VPB[1] VCLK VPB[0] VPA[7] VPA[6] VPA[5] VDDD(3V3) VSSD VSSC VDDC(1V8) VPA[4] VPA[3] VPA[2] VPA[1] VPA[0] DE/FREF
[1]
TDA9981B_1
P = power supply; G = ground; I = input; O = output.
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 4 July 2008
7 of 41
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
8. Functional description
The TDA9981B is designed to convert digital data (video and audio) into an HDMI or a DVI stream. This HDMI stream can handle RGB, YCbCr 4 : 4 : 4 and YCbCr 4 : 2 : 2. The TDA9981B can accept at its inputs any of the following video modes:
* * * *
RGB YCbCr 4 : 4 : 4 YCbCr 4 : 2 : 2 semi-planar YCbCr 4 : 2 : 2 ITU656 and ITU656-like
It can also handle audio. The TDA9981B can accept at its inputs any of the following audio buses:
* I2S-bus (4 lines): up to 8 audio channels * S/PDIF (1 channel): L-PCM (IEC 60958) or compressed audio (IEC 61937) 8.1 System clock
The clock management is based on a set of two PLLs that generate the different clocks required inside the chip:
* PLL double edge can generate a clock at twice the VCLK input frequency to capture
the data at the video input formatter.
* PLL serializer is a system clock generator, which enables the stream produced by the
encoder to be transmitted on the HDMI data channel at ten times the sampling rate or more; see Section 8.14.2.
8.2 Video input processor
The TDA9981B has three video input ports VPA[7:0], VPB[7:0] and VPC[7:0]. The TDA9981B can reallocate and swap each of the 3 input channel ports by inverting the bus and swapping each port. The TDA9981B can be set to latch data at either the rising or falling edge or both. The video input formats accept (see Table 5):
* * * *
RGB YCbCr 4 : 4 : 4 (up to 3 x 8-bit) YCbCr 4 : 2 : 2 semi-planar (up to 2 x 12-bit) YCbCr 4 : 2 : 2 compliant with ITU656 and ITU656-like (up to 1 x 12-bit)
TDA9981B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 4 July 2008
8 of 41
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Product data sheet Rev. 01 -- 4 July 2008 [1]
(c) NXP B.V. 2008. All rights reserved. TDA9981B_1
NXP Semiconductors
Table 5. Color space RGB
Inputs of video input formatter Format Channels Sync Rising edge X X X X X X X X X X X X X X X X X X SMPTE293M SMPTE293M ITU656-like ITU656-like ITU656-like ITU656-like ITU656-like ITU656-like Falling edge Double edge[1] Transmission Max. pixel clock Max. input input format on pin VCLK format (MHz) 150 150 150 150 150 150 150 150 54.054 54.054 27.027 54.054 54.054 27.027 148.5 148.5 148.5 148.5 480p/576p 480p/576p 480p/576p 480p/576p 480p/576p 480p/576p 1080p 1080p 1080p 1080p Table 13 Table 11 Table 12 Table 9 Table 10 Table 8 Table 7 Reference
4:4:4
3 x 8-bit
external external embedded embedded
Table 6
YCbCr
4:4:4
3 x 8-bit
external external embedded embedded
YCbCr
4:2:2
up to 1 x 12-bit ITU656-like
external external external embedded embedded embedded
up to 2 x 12-bit semi-planar
external external embedded embedded
150 MHz pixel rate HDMI transmitter
Double edge means both rising and falling edges.
TDA9981B
9 of 41
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
Table 6. RGB 4 : 4 : 4 mappings RGB 4 : 4 : 4 (3 x 8-bit) external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] RGB 4 : 4 : 4 B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] RGB 4 : 4 : 4 G[0] G[1] G[2] G[3] G[4] G[5] G[6] G[7] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] RGB 4 : 4 : 4 R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF RGB 4 : 4 : 4 used used used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF VPA[7:0] B0 B1 B2 B3 ... Bxxx Bxxx
VPB[7:0]
G0
G1
G2
G3
...
Gxxx
Gxxx
VPC[7:0]
R0
R1
R2
R3
...
Rxxx
Rxxx
001aag380
DE could also be generated from HSYNC/HREF and VSYNC/VREF
Fig 3.
Pixel encoding in RGB 4 : 4 : 4 (rising edge) input
TDA9981B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 4 July 2008
10 of 41
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
Table 7. YCbCr 4 : 4 : 4 mappings YCbCr 4 : 4 : 4 (3 x 8-bit) external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCbCr 4 : 4 : 4 CB[0] CB[1] CB[2] CB[3] CB[4] CB[5] CB[6] CB[7] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 4 : 4 Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] YCbCr 4 : 4 : 4 CR[0] CR[1] CR[2] CR[3] CR[4] CR[5] CR[6] CR[7] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4 : 4 : 4 used used used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF VPA[7:0] Cb0 Cb1 Cb2 Cb3 ... Cbxxx CBxxx
VPB[7:0]
Y0
Y1
Y2
Y3
...
Yxxx
Yxxx
VPC[7:0]
Cr0
Cr1
Cr2
Cr3
...
Crxxx
Crxxx
001aai431
DE could also be generated from HSYNC/HREF and VSYNC/VREF
Fig 4.
Pixel encoding in YCbCr 4 : 4 : 4 (rising edge) input
TDA9981B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 4 July 2008
11 of 41
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
Table 8. YCbCr 4 : 2 : 2 ITU656-like external synchronization single edge mappings YCbCr : 2 : 2 ITU656-like external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCbCr 4 : 2 : 2 (ITU656-like) CB[0] CB[1] CB[2] CB[3] Y0[0] Y0[1] Y0[2] Y0[3] CR[0] CR[1] CR[2] CR[3] Y1[0] Y1[1] Y1[2] Y1[3] Video port B Pin YCbCr 4 : 2 : 2 (ITU656-like) Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] VPB[0] CB[4] VPB[1] CB[5] VPB[2] CB[6] VPB[3] CB[7] VPB[4] CB[8] VPB[5] CB[9] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4 : 2 : 2 used used used
VPB[6] CB[10] Y0[10] CR[10] Y1[10] VPB[7] CB[11] Y0[11] CR[11] Y1[11]
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF Cb0 Y0 Cr0 Y1 ... Crxxx Yxxx
VPB[7:0]; VPA[3:0]
001aai434
Fig 5.
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization single edge (rising edge) input
TDA9981B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 4 July 2008
12 of 41
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
Table 9. YCbCr 4 : 2 : 2 ITU656-like external synchronization double edge mappings YCbCr 4 : 2 : 2 ITU656-like external synchronization double edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr 4 : 2 : 2 (ITU656-like) Y0[0] Y0[1] Y0[2] Y0[3] CR[0] CR[1] CR[2] CR[3] Y1[0] Y1[1] Y1[2] Y1[3] VPA[0] CB[0] VPA[1] CB[1] VPA[2] CB[2] VPA[3] CB[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 2 : 2 (ITU656-like) CB[4] CB[5] CB[6] CB[7] CB[8] CB[9] CB[10] CB[11] Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] CR[10] CR[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4 : 2 : 2 used used used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF Cb0 Y0 Cr0 Y1 ... Crxxx Yxxx
VPB[7:0]; VPA[3:0]
001aai432
Fig 6.
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like external synchronization double edge (rising and falling) input
TDA9981B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 4 July 2008
13 of 41
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
Table 10. YCbCr 4 : 2 : 2 ITU656-like embedded synchronization single edge mappings YCbCr 4 : 2 : 2 ITU656-like embedded synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr 4 : 2 : 2 (ITU656-like) Y0[0] Y0[1] Y0[2] Y0[3] CR[0] CR[1] CR[2] CR[3] Y1[0] Y1[1] Y1[2] Y1[3] VPA[0] CB[0] VPA[1] CB[1] VPA[2] CB[2] VPA[3] CB[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 2 : 2 (ITU656-like) CB[4] CB[5] CB[6] CB[7] CB[8] CB[9] CB[10] CB[11] Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] CR[10] CR[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4 : 2 : 2 not used not used not used
VCLK
VPB[7:0]; VPA[3:0]
Cb0
Y0
Cr0
Y1
...
Crxxx
Yxxx
001aai436
Fig 7.
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization single edge (rising edge) input
TDA9981B_1
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NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
Table 11. YCbCr 4 : 2 : 2 ITU656-like embedded synchronization double edge mappings YCbCr 4 : 2 : 2 ITU656-like embedded synchronization double edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h. Video port A Pin YCbCr 4 : 2 : 2 (ITU656-like) Y0[0] Y0[1] Y0[2] Y0[3] CR[0] CR[1] CR[2] CR[3] Y1[0] Y1[1] Y1[2] Y1[3] VPA[0] CB[0] VPA[1] CB[1] VPA[2] CB[2] VPA[3] CB[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 2 : 2 (ITU656-like) CB[4] CB[5] CB[6] CB[7] CB[8] CB[9] CB[10] CB[11] Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] CR[10] CR[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4 : 2 : 2 not used not used not used
VCLK
VPB[7:0]; VPA[3:0]
Cb0
Y0
Cr0
Y1
...
Crxxx
Yxxx
001aai435
Fig 8.
Pixel encoding YCbCr 4 : 2 : 2 ITU656-like embedded synchronization double edge (rising and falling) input
TDA9981B_1
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NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
Table 12. YCbCr 4 : 2 : 2 semi-planar external synchronization mappings YCbCr 4 : 2 : 2 semi-planar external synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCbCr 4 : 2 : 2 semi-planar Y0[0] Y0[1] Y0[2] Y0[3] CB[0] CB[1] CB[2] CB[3] Y1[0] Y1[1] Y1[2] Y1[3] CR[0] CR[1] CR[2] CR[3] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 2 : 2 semi-planar Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] YCbCr 4 : 2 : 2 semi-planar CB[4] CB[5] CB[6] CB[7] CB[8] CB[9] CB[10] CB[11] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] CR[10] CR[11] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4:2:2 used used used
VCLK
CONTROL INPUTS
HSYNC/HREF VSYNC/VREF DE/FREF Y0 Y1 Y2 Y3 Y4 Y5 ...
VPB[7:0]; VPA[3:0]
VPC[7:0]; VPA[7:4]
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
...
001aai437
Fig 9.
Pixel encoding YCbCr 4 : 2 : 2 semi-planar external synchronization (rising edge) input
TDA9981B_1
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NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
Table 13. YCbCr 4 : 2 : 2 semi-planar embedded synchronization mappings YCbCr 4 : 2 : 2 semi-planar embedded synchronization single edge. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Video port A Pin VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] YCbCr 4 : 2 : 2 semi-planar Y0[0] Y0[1] Y0[2] Y0[3] CB[0] CB[1] CB[2] CB[3] Y1[0] Y1[1] Y1[2] Y1[3] CR[0] CR[1] CR[2] CR[3] Video port B Pin VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] YCbCr 4 : 2 : 2 semi-planar Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] Video port C Pin VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7] YCbCr 4 : 2 : 2 semi-planar CB[4] CB[5] CB[6] CB[7] CB[8] CB[9] CB[10] CB[11] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] CR[10] CR[11] Control Pin HSYNC/HREF VSYNC/VREF DE/FREF YCbCr 4:2:2 not used not used not used
VCLK
VPB[7:0]; VPA[3:0]
Y0
Y1
Y2
Y3
Y4
Y5
...
VPC[7:0]; VPA[7:4]
Cb0
Cr0
Cb2
Cr2
Cb4
Cr4
...
001aai438
Fig 10. Pixel encoding YCbCr 4 : 2 : 2 semi-planar embedded synchronization (rising edge) input
TDA9981B_1
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TDA9981B
150 MHz pixel rate HDMI transmitter
8.3 Synchronization
The TDA9981B can be synchronized with Hsync/Vsync external inputs or with extraction of the sync information from embedded sync (SAV/EAV) codes inside the video stream.
8.3.1 Timing extraction generator
This block can extract the synchronization signals Href, Vref and Fref from Start Active Video (SAV) and End Active Video (EAV) in case of embedded synchronization in the data stream. Synchronization signals can be embedded in RGB, YCbCr 4 : 4 : 4, YCbCr 4 : 2 : 2 semi-planar (up to 2 x 12-bit), YCbCr 4 : 2 : 2 ITU656 and ITU656-like (up to 1 x 12-bit).
8.3.2 Data enable generator
The TDA9981B contains a Data Enable (DE) generator; this can generate an internal DE signal for a system which does not provide one.
8.4 Input and output video format
Due to the flexible video input formatter, the TDA9981B can accept a large range of input formats. This flexibility allows the TDA9981B to be compatible with the maximum possible number of MPEG decoders. Moreover, these input formats may be changed in many ways (color space converter, upsampler and downsampler) to be transmitted across the HDMI link. Table 14 gives the possible inputs and outputs.
Table 14. Input Color space RGB Format 4:4:4 Channels 3 x 8-bit Use of color space converter, upsampler and downsampler Output Color space RGB YCbCr YCbCr YCbCr 4:4:4 3 x 8-bit RGB YCbCr YCbCr YCbCr 4:2:2 up to 1 x 12-bit YCbCr YCbCr RGB up to 2 x 12-bit YCbCr YCbCr RGB Format 4:4:4 4:2:2 4:4:4 4:4:4 4:2:2 4:4:4 4:2:2 4:4:4 4:4:4 4:2:2 4:4:4 4:4:4 Channels 3 x 8-bit 2 x 12-bit 3 x 8-bit 3 x 8-bit 2 x 12-bit 3 x 8-bit 2 x 12-bit 3 x 8-bit 3 x 8-bit 2 x 12-bit 3 x 8-bit 3 x 8-bit
8.5 Upsampler
The incoming YCbCr 4 : 2 : 2 (2 x 12-bit) data stream format could be upsampled into a 12-bit YCbCr 4 : 4 : 4 (3 x 12-bit) data stream by repeating or linearly interpolating the chrominance pixels.
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TDA9981B
150 MHz pixel rate HDMI transmitter
8.6 Color space converter
The color space converter is used to convert input video data from one type to another color space (RGB to YCbCr and YCbCr to RGB). This block can be bypassed and each coefficient is programmable via the I2C-bus register. Oin G\Y C 11 C 12 C 13 G\Y Y \G R\C + Oin C B \R = C 21 C 22 C 23 x R\C B B C R \B C 31 C 32 C 33 B\C R Oin B\C
R
Oout Y \G + Oout C B \R Oout C \B R
8.7 Downsampler
This block works only with YCbCr input format; these filters downsample the CB and CR signals by a factor 2. A delay is added on the G/Y channel, which corresponds to the pipeline delay of the filters, to put the Y channel in phase with the CB-CR channel.
8.8 Audio input format
The TDA9981B is compatible with HDMI 1.2a (DVD support). The TDA9981B can carry audio in I2S-bus format (one stereo up to four stereo channels) or in S/PDIF format. S/PDIF or I2S-bus format can be selected via the I2C-bus. Only one audio format can be used at a time: either S/PDIF or I2S-bus. Table 15 shows the audio port allocation.
Table 15. Audio port configuration All audio ports are LV-TTL compatible. Audio port AP0 AP1 AP2 AP3 AP4 AP5 AP6 AP7 ACLK I2S-bus and S/PDIF input configuration WS (word select) I2S-bus port 0 I2S-bus port 1 I2S-bus port 2 I2S-bus port 3 MCLK (master clock for S/PDIF) S/PDIF input AUX (internal test) SCK (I2S-bus clock)
8.9 S/PDIF
The audio port AP6 is used for the S/PDIF feature. In this format the TDA9981B supports 2-channel uncompressed PCM data (IEC 60958) layout 0 or compressed bit stream up to 8 multichannels (Dolby Digital, DTS, AC-3, etc.) layout 1. The TDA9981B is able to recover the original clock from the S/PDIF signal (no need for an external clock). In addition it can also use an external clock (MCLK) to decode the S/PDIF signal.
8.10 I2S-bus
The TDA9981B supports the NXP I2S-bus format. There are four I2S-bus stereo input channels (AP1 to AP4), which enable 8 uncompressed audio channels to be carried. The I2S-bus input interface receives an I2S-bus signal including serial data, word select and
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TDA9981B
150 MHz pixel rate HDMI transmitter
serial clock. Various I2S-bus formats are supported and can be selected by setting the appropriate bits of the register. The I2S-bus input interface can receive up to 24-bit wide audio samples via the serial data input with a clock frequency of at least 32 times the input sample frequency fs. Since the I2S-bus format is MSB aligned, audio data with an arbitrary precision can be received automatically. Audio samples with a precision better than 24 bits are truncated to 24 bits. If the input clock has a frequency of 32 x fs, only 16-bit audio samples can be received. In this case, the 8 LSBs will be set to logic 0. The serial data signal carries the serial baseband audio data, sample by sample left/right interleaved. The word select signal WS indicates whether left or right channel information is transferred over the serial data line. The formats for 16-bit and 32-bit modes are shown in Figure 11.
AP0/WS
left channel
right channel
ACLK 0R B23L B0L 0L 0L 0L B23R B0R 0R 0R 0R B23L
001aag915
APx x = 1, 2, 3, 4
a. 32-bit mode
AP0/WS
left channel
right channel
ACLK B0R B15L B14L B13L B2L B1L B0L B15R B14R B13R B2R B1R B0R B15L
001aag916
APx x = 1, 2, 3, 4
b. 16-bit mode Fig 11. NXP I2S-bus formats
8.11 Power management
The TDA9981B can be powered down via the I2C-bus register.
8.12 Interrupt controller
Pin INT is used to alert the microcontroller that a critical event concerning the HDMI has occurred (hot plug detect, RxSense). These interrupts are maskable. Hot plug or unplug detect: pin HPD is the hot plug detection pin; it is 5 V input tolerant.
8.13 Initialization
Hard reset: after power-up, the TDA9981B is activated by a hard reset via pin RST_N. However, the TDA9981B has a power-on reset.
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TDA9981B
150 MHz pixel rate HDMI transmitter
8.14 HDMI
8.14.1 Output HDMI buffers
An external resistor must be used to set the HDMI output amplitude. It has to be connected between pin EXT_SWING and VDDH(3V3).
8.14.2 Pixel repetition
To transmit video formats with pixel rates below 25 MHz or to increase the number of audio sample packets in each frame, the TDA9981B uses pixel repetition to increase the transmitted pixel clock.
Table 16. 0 0 0 0 0 0 0 0 1 1 1 1 Pixel repetition PIX_REP[2] 0 0 0 0 1 1 1 1 0 0 0 1 PIX_REP[1] 0 0 1 1 0 0 1 1 0 0 1 x PIX_REP[0] 0 1 0 1 0 1 0 1 0 1 x x Pixel repeated no repetition once twice 3 times 4 times 5 times 6 times 7 times 8 times 9 times undefined undefined
PIX_REP[3]
8.14.3 HDMI and DVI receiver discrimination
This information is located in the E-EDID receiver part, in the 'Vendor-Specific Datablock' within the first CEA EDID timing extension. If the 24-bit IEEE registration identifier contains the value 00 0C03h, then the receiver will support HDMI, otherwise the device will be treated as a DVI device. However, the TDA9981B does not have direct access to that information since E-EDID is read by an external microprocessor through the TDA9981B I2C-bus gate.
8.14.4 DDC channel
The DDC-bus pins DDC_SDA and DDC_SCL are 5 V tolerant and can work at standard mode (100 kHz). 8.14.4.1 E-EDID reading In order to get receiver capabilities, the TDA9981B must read the E-EDID of the receiver. This is made possible by temporarily connecting the I2C-bus to the DDC lines, so that the microprocessor is able to read full EDID.
8.14.5 RxSense detection
The TDA9981B is able to sense the connectivity and working behavior of the receiver. The RxSense detection feature detects the presence of the 50 pull-up resistor RT on the TMDS clock channel of the downstream site.
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TDA9981B
150 MHz pixel rate HDMI transmitter
VDDA
RT RT
TRANSMITTER Z0 D D RECEIVER
001aag601
Fig 12. Receiver sensitivity detection
As long as the receiver is connected to the transmitter and powered up, bit RXS_FIL is set to logic 1. When the cable is unplugged or the receiver site is powered off (assuming in this case that VDD is switched off), the RxSense generates an interrupt inside the TDA9981B, changing the value of bit RXS_FIL to logic 0. This allows the application to stop sending unnecessary video content. This feature is very useful when the receiver has recovered from an off state and does not generate an HPD HIGH-to-LOW-to-HIGH transition. In this particular case, RxSense will generate an interrupt so that the TDA9981B restarts sending video. Remark: According to the HDMI specification, only the HPD interrupt allows the application to read the EDID. It is not mandatory to use RxSense to initialize the EDID reading procedure.
8.15 I2C-bus interface
The I2C-bus pins I2C_SDA and I2C_SCL are 5 V tolerant and can work at fast mode (400 kHz).
9. I2C-bus register definitions
9.1 I2C-bus protocol
The registers of the TDA9981B can be accessed via the I2C-bus. The TDA9981B is used as a slave device and both the fast mode 400 kHz and the standard mode 100 kHz are supported. Bits A0 and A1 of the I2C-bus device address are externally selected by pins A0 and A1. The I2C-bus device address is given in Table 17.
Table 17. A6 1 Device address R/W A4 1 A3 0 A2 0 A1 A1 A0 A0 1/0 A5 1
Device address
The I2C-bus access format is shown in Figure 13.
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TDA9981B
150 MHz pixel rate HDMI transmitter
For read access, the master writes the address of the TDA9981B, the subaddress to access the specific register and then the data.
123456789123456789123456789 SCL SDA SLAVE ADDRESS SUBADDRESS DATA STOP
001aaf292
Fig 13. I2C-bus access
10. Limiting values
Table 18. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD(3V3) VDD(1V8) VDD Tstg Tamb Tj Vesd Parameter supply voltage (3.3 V) supply voltage (1.8 V) supply voltage difference storage temperature ambient temperature junction temperature electrostatic discharge voltage HBM Conditions Min -0.5 -0.5 -0.5 -55 0 -2000 Max +4.6 +2.5 +0.5 +150 85 125 +2000 Unit V V V C C C V
11. Thermal characteristics
Table 19. Symbol Rth(j-a) Rth(j-c) Thermal characteristics Parameter Conditions Typ 50.6 16.2 Unit K/W K/W thermal resistance from junction in free air; JEDEC 4L board to ambient thermal resistance from junction to case
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TDA9981B
150 MHz pixel rate HDMI transmitter
12. Static characteristics
Table 20. Supplies VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 C to 85 C. Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 C; unless otherwise specified. Symbol VDDA(FRO_3V3) VDDA(PLL_3V3) VDDD(3V3) VDDH(3V3) VDDC(1V8) IDDA(FRO_3V3) IDDA(PLL_3V3) IDDD(3V3) IDDH(3V3) IDDC(1V8) fclk(max) Pcons Ptot Ppd IDDA(FRO_3V3) IDDA(PLL_3V3) IDDD(3V3) IDDH(3V3) IDDC(1V8) fclk(max) Pcons Ptot Ppd
[1] [2]
Parameter free running oscillator 3.3 V analog supply voltage PLL 3.3 V analog supply voltage digital supply voltage (3.3 V) HDMI supply voltage (3.3 V) core supply voltage (1.8 V) free running oscillator 3.3 V analog supply current PLL 3.3 V analog supply current digital supply current (3.3 V) HDMI supply current (3.3 V) core supply current (1.8 V) maximum clock frequency power consumption total power dissipation power dissipation in Power-down mode free running oscillator 3.3 V analog supply current PLL 3.3 V analog supply current digital supply current (3.3 V) HDMI supply current (3.3 V) core supply current (1.8 V) maximum clock frequency power consumption total power dissipation power dissipation in Power-down mode
Conditions
Min 3.0 3.0 3.0 3.0 1.65 [1]
Typ 3.3 3.3 3.3 3.3 1.8 3.5 14 94 235 369 14 4 14 175 381.5 515.5 14
Max 3.6 3.6 3.6 3.6 1.95 0.5 4.5 1.5 14.5 107.5 288 438 19 0.5 5 3.5 15 200 468 618 19
Unit V V V V V mA mA mA mA mA MHz mW mW mW mA mA mA mA mA MHz mW mW mW
TDA9981BHL/8 and TDA9981BHL/15
TDA9981BHL/8; up to 81 MHz [1] [1] [1] [1]
81 -
TDA9981BHL/15; up to 150 MHz
[2]
-
[2] [2] [2] [2]
150 -
Worst case: video input format: 720p at 60 Hz (RGB 4 : 4 : 4 embedded sync), video output format: 720p at 60 Hz (YCbCr 4 : 4 : 4). Video input format: 1080p (RGB 4 : 4 : 4 embedded sync, rising edge), video output format: 1080p (RGB 4 : 4 : 4).
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TDA9981B
150 MHz pixel rate HDMI transmitter
Table 21. LV-TTL digital inputs and outputs VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 C to 85 C. Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 C; unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit Not 5 V tolerant inputs: pins HSYNC, VSYNC, AP[7:0], ACLK, TM, A0, A1, VPA[7:0], VPB[7:0], VPC[7:0], VCLK, DE and RST_N VIL VIH IIL IIH Ci VIL VIH Ci VOL LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input capacitance LOW-level input voltage HIGH-level input voltage input capacitance LOW-level output voltage CL = 10 pF; IOL = 2 mA 2.0 -1 -1 2.0 4.5 4.5 0.8 +1 +1 0.8 0.4 V V A A pF V V pF V
5 V tolerant input: pin HPD
Output: pin INT
Table 22. TMDS outputs VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 C to 85 C. Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 C; unless otherwise specified. Symbol Vo(p-p) VOH VOL Parameter peak-to-peak output voltage HIGH-level output voltage LOW-level output voltage Conditions single output; Rext = 610 (1 % tolerance) with test load and operating condition as in HDMI 1.2a specification Min 400 3.125 2.535 Typ 510 3.3 2.79 Max 600 3.475 3.065 Unit mV V V TMDS output pins: TX0-, TX0+, TX1-, TX1+, TX2-, TX2+, TXC- and TXC+
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150 MHz pixel rate HDMI transmitter
13. Dynamic characteristics
Table 23. Timing characteristics VDDA(FRO_3V3) = 3.0 V to 3.6 V; VDDA(PLL_3V3) = 3.0 V to 3.6 V; VDDH(3V3) = 3.0 V to 3.6 V; VDDD(3V3) = 3.0 V to 3.6 V; VDDC(1V8) = 1.65 V to 1.95 V; VPP = 0 V; Tamb = 0 C to 85 C. Typical values are measured at VDDA(FRO_3V3) = VDDA(PLL_3V3) = VDDH(3V3) = VDDD(3V3) = 3.3 V; VDDC(1V8) = 1.8 V; VPP = 0 V and Tamb = 25 C; unless otherwise specified. Symbol fclk(max) tsu(D) th(D) clk DDC fSCL Ci I2C-bus; fSCL Ci fclk(max) Parameter maximum clock frequency data input set-up time data input hold time clock duty cycle I2C-bus; 5 V tolerant; master bus: pins DDC_SDA and DDC_SCL standard mode standard mode fast mode capacitance for each I/O pin maximum clock frequency TDA9981BHL/8 TDA9981BHL/15 TMDS output pins: TX0-, TX0+, TX1-, TX1+, TX2- and TX2+ fclk(max) maximum clock frequency TDA9981BHL/8 TDA9981BHL/15
[1] clk = tclk(H) / (tclk(H) + tclk(L)).
[1]
Conditions TDA9981BHL/8 TDA9981BHL/15
Min 81 150 -0.25 2.20 40
Typ 7 7 -
Max 60 100 100 400 -
Unit MHz MHz ns ns % kHz pF kHz kHz pF MHz MHz MHz GHz
Clock inputs: pins VCLK, VPA[7:0], VPB[7:0] and VPC[7:0]; see Figure 14, 15, 17 and 18
SCL clock frequency capacitance for each I/O pin
5 V tolerant; master bus: pins I2C_SDA and I2C_SCL SCL clock frequency 81 150 810 1.5
TMDS output pins: TXC- and TXC+
TDA9981B_1
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Product data sheet
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NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
13.1 Input format
In Table 24 the port VPA has been mapped to CB (YUV space)/B (RGB space), VPB has been mapped to Y (YUV space)/G (RGB space) and VPC has been mapped to CR (YUV space)/R (RGB space).
Table 24. Input pins Video port A VPA[0] VPA[1] VPA[2] VPA[3] VPA[4] VPA[5] VPA[6] VPA[7] Video port B VPB[0] VPB[1] VPB[2] VPB[3] VPB[4] VPB[5] VPB[6] VPB[7] Video port C VPC[0] VPC[1] VPC[2] VPC[3] VPC[4] VPC[5] VPC[6] VPC[7]
[1] [2] [3] [4]
Input format Signal RGB 4:4: CB[0]/B[0] CB[1]/B[1] CB[2]/B[2] CB[3]/B[3] CB[4]/B[4] CB[5]/B[5] CB[6]/B[6] CB[7]/B[7] Y[0]/G[0] Y[1]/G[1] Y[2]/G[2] Y[3]/G[3] Y[4]/G[4] Y[5]/G[5] Y[6]/G[6] Y[7]/G[7] CR[0]/R[0] CR[1]/R[1] CR[2]/R[2] CR[3]/R[3] CR[4]/R[4] CR[5]/R[5] CR[6]/R[6] CR[7]/R[7] B[0] B[1] B[2] B[3] B[4] B[5] B[6] B[7] G[0] G[1] G[2] G[3] G[4] G[5] G[6] G[7] R[0] R[1] R[2] R[3] R[4] R[5] R[6] R[7] 4[1] YUV 4 : 4 : 4[2] CB[0] CB[1] CB[2] CB[3] CB[4] CB[5] CB[6] CB[7] Y[0] Y[1] Y[2] Y[3] Y[4] Y[5] Y[6] Y[7] CR[0] CR[1] CR[2] CR[3] CR[4] CR[5] CR[6] CR[7] 4 : 2 : 2 (semi-planar)[3] 4 : 2 : 2 (ITU656-like)[4] Y0[0] Y0[1] Y0[2] Y0[3] CB[0] CB[1] CB[2] CB[3] Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] CB[4] CB[5] CB[6] CB[7] CB[8] CB[9] CB[10] CB[11] Y1[0] Y1[1] Y1[2] Y1[3] CR[0] CR[1] CR[2] CR[3] Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9] Y1[10] Y1[11] CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] CR[10] CR[11] CB[0] CB[1] CB[2] CB[3] L L L L CB[4] CB[5] CB[6] CB[7] CB[8] CB[9] CB[10] CB[11] L L L L L L L L Y0[0] Y0[1] Y0[2] Y0[3] L L L L Y0[4] Y0[5] Y0[6] Y0[7] Y0[8] Y0[9] Y0[10] Y0[11] L L L L L L L L CR[0] CR[1] CR[2] CR[3] L L L L CR[4] CR[5] CR[6] CR[7] CR[8] CR[9] Y1[0] Y1[1] Y1[2] Y1[3] L L L L Y1[4] Y1[5] Y1[6] Y1[7] Y1[8] Y1[9]
CR[10] Y1[10] CR[11] Y1[11] L L L L L L L L L L L L L L L L
Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 45h; VIP_CNTRL_2 = 01h. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 14h. Register VIP_CNTRL_0 = 23h; VIP_CNTRL_1 = 50h; VIP_CNTRL_2 = 00h.
TDA9981B_1
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TDA9981B
150 MHz pixel rate HDMI transmitter
13.2 Example of supported video
The TDA9981B supports all EIA/CEA-861B, ATSC video input formats.
Table 25. Format nr. Timing parameters for EIA/CEA-861B Format V frequency (Hz) 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 59.9401 60 60 60 60 60 60 60 60 60 60 60 60 50 50 50 50 50 50 H total V total H frequency (kHz) 31.4685 31.4685 44.955 33.7163 15.7343 15.7043 15.7642 15.7343 15.7043 15.7642 31.4685 67.4326 31.5 31.5 45 33.75 15.75 15.72 15.78 15.75 15.72 15.78 31.5 67.5 31.25 37.5 28.125 15.625 15.6 15.65 Pixel frequency (MHz) 25.174825 27 74.175824 74.175824 13.5 13.474286 13.525714 13.5 13.474286 13.525714 54 148.35165[1] 25.2 27.27 74.25 74.25 13.5135 13.48776 13.53924 13.5135 13.48776 13.53924 54.054 148.5[1] 27 74.25 74.25 13.5 13.4784 13.5216 Pixel repetition
59.94 Hz systems 1 (VGA) 2, 3 4 5 6, 7 (NTSC) 8, 9 8, 9 10, 11 12, 13 12, 13 14, 15 16[1] 60 Hz systems 1 (VGA) 2, 3 4 5 6, 7 (NTSC) 8, 9 8, 9 10, 11 12, 13 12, 13 14, 15 16[1] 50 Hz systems 17, 18 19 20 21, 22 (PAL) 23, 24 23, 24
TDA9981B_1
640 x 480p 720 x 480p 1280 x 720p 1920 x 1080i 720 x 480i 720 x 240p 720 x 240p 720 x 480i 720 x 240p 720 x 240p 1440 x 480p 1920 x 1080p 640 x 480p 720 x 480p 1280 x 720p 1920 x 1080i 720 x 480i 720 x 240p 720 x 240p 720 x 480i 720 x 240p 720 x 240p 1440 x 480p 1920 x 1080p 720 x 576p 1280 x 720p 1920 x 1080i 720 x 576i 720 x 288p 720 x 288p
800 858 1650 2200 858 858 858 858 858 858 1716 2200 800 858 1650 2200 858 858 858 858 858 858 1716 2200 864 1980 2640 864 864 864
525 525 750 1125 525 262 263 525 262 263 525 1125 525 525 750 1125 525 262 263 525 262 263 525 1125 625 750 1125 625 312 313
1 1 1 1 2 2 2 4, 5, 7[1], 8[1], 10[1] 4, 5, 7[1], 8[1], 10[1] 4, 5, 7[1], 8[1], 10[1] 2 1 1 1 1 1 2 2 2 4, 5, 7[1], 8[1], 10[1] 4, 5, 7[1], 8[1], 10[1] 4, 5, 7[1], 8[1], 10[1] 2 1 1 1 1 2 2 2
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TDA9981B
150 MHz pixel rate HDMI transmitter
Table 25. Format nr. 23, 24 25, 26 27, 28 27, 28 27, 28 29, 30 31[1] 32 32 33 34 34
[1]
Timing parameters for EIA/CEA-861B ...continued Format 720 x 288p 720 x 576i 720 x 288p 720 x 288p 720 x 288p 1440 x 576p 1920 x 1080p 1920 x 1080p 1920 x 1080p 1920 x 1080p 1920 x 1080p 1920 x 1080p V frequency (Hz) 50 50 50 50 50 50 50 23.976 24 25 29.97 30 H total 864 864 864 864 864 1728 2640 2750 2750 2640 2200 2200 V total 314 625 312 313 314 625 1125 1125 1125 1125 1125 1125 H frequency (kHz) 15.7 15.625 15.6 15.65 15.7 31.25 56.25 26.973 27 28.125 33.716 33.75 Pixel frequency (MHz) 13.5648 13.5 13.4784 13.5216 13.5648 54 148.5[1] 74.175824 74.25 74.25 74.175824 74.25 Pixel repetition 2 4, 5, 7[1], 8[1], 10[1] 4, 5, 7[1], 8[1], 10[1] 4, 5, 7[1], 8[1], 10[1] 2 1 1 1 1 1 1 1
Various systems
Only for TDA9981BHL/15.
Table 26. Standard
Timing parameters for PC standards below 150 MHz Format 640 x 350p 640 x 400p 720 x 400p V frequency (Hz) 85.080 85.080 85.039 59.940 72.809 75.000 85.008 56.250 60.317 72.188 75.000 85.061 119.972 60.000 60.004 70.069 75.029 84.997 86.957 H total 832 832 936 800 832 840 832 1024 1056 1040 1056 1048 960 1088 1344 1328 1312 1376 1264 V total 445 445 446 525 520 500 509 625 628 666 625 631 636 517 806 806 800 808 817 H frequency (kHz) 37.861 37.861 37.927 31.469 37.861 37.500 43.269 35.156 37.879 48.077 46.875 53.674 76.302 31.020 48.363 56.476 60.023 68.677 35.522 Pixel frequency Pixel (MHz) repetition 31.500 31.500 35.500 25.175 31.500 31.500 36.000 36.000 40.000 50.000 49.500 56.250 73.250 33.750 65.000 75.000 78.750 94.500 44.900 -
0.31M3 VGA
640 x 480p 640 x 480p 640 x 480p 640 x 480p
0.48M3 SVGA
800 x 600p 800 x 600p 800 x 600p 800 x 600p 800 x 600p
0.48M3-R 0.41M9 0.79M3 XGA
800 x 600p 848 x 480p 1024 x 768p 1024 x 768p 1024 x 768p 1024 x 768p[1] 1024 x 768i
TDA9981B_1
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TDA9981B
150 MHz pixel rate HDMI transmitter
Table 26. Standard 0.79M3-R XGA[1] 1.00M3[1] 0.98M9-R 0.98M9
Timing parameters for PC standards below 150 MHz ...continued Format 1024 x 768p[1] 1152 x 864p[1] 1280 x 768p 1280 x 768p[1] 1280 x 768p 1280 x 768p[1] 1280 x 768p[1] V frequency (Hz) 119.989 75.000 59.995 119.798 59.870 74.893 84.837 59.910 119.909 59.810 74.934 84.880 60.000 85.002 60.020 75.025 60.015 119.967 59.948 59.978 59.901 59.887 74.984 59.883 59.954 H total 1184 1600 1440 1440 1664 1696 1712 1440 1440 1680 1696 1712 1800 1728 1688 1688 1792 1520 1560 1864 1600 1904 1936 1840 2240 V total 813 900 790 813 798 805 809 823 847 831 838 843 1000 1011 1066 1066 795 813 1080 1089 926 934 942 1080 1089 H frequency (kHz) 97.551 67.500 47.396 97.396 47.776 60.289 68.633 49.306 101.563 49.702 62.795 71.554 60.000 85.938 63.981 79.976 47.712 97.533 64.744 65.317 55.469 55.935 70.635 64.674 65.290 Pixel frequency Pixel (MHz) repetition 115.500 108.000 68.250 140.250 79.500 102.250 117.500 71.000 146.250 83.500 106.500 122.500 108.000 148.500 108.000 135.000 85.500 148.250 101.000 121.750 88.750 106.500 136.750 119.000 146.250 -
1.02MA-R 1.02MA[1]
1280 x 800p 1280 x 1280 x 1280 x 800p[1] 800p[1] 800p[1] 960p[1] 960p[1] 1024p[1] 768p[1] 768p[1] 1050p[1] 900p[1] 900p[1] 1050p[1] 1050p[1]
1280 x 800p[1] 1.23M3[1] 1.31M4 SXGA[1] 1.04M9[1] 1.04M9-R[1] 1.47M3[1] 1.29MA-R[1] 1.29MA[1] 1.76MA-R[1] 1.76MA[1]
[1]
1280 x 1280 x 1280 x 1360 x 1360 x 1400 x 1440 x 1440 x 1680 x 1680 x
1280 x 1024p[1]
1.47M3-R[1] 1400 x 1050p[1]
1440 x 900p[1]
Only for TDA9981BHL/15.
TDA9981B_1
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TDA9981B
150 MHz pixel rate HDMI transmitter
13.3 Timing diagrams
VCLK tclk(H) tclk(L) CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF VPA[7:0] B0 B1 B2 B3 ... Bxxx Bxxx
VPB[7:0]
G0
G1
G2
G3
...
Gxxx
Gxxx
VPC[7:0]
R0 th(D) tsu(D)
R1
R2
R3
...
Rxxx
Rxxx
001aag250
Fig 14. Timing RGB 4 : 4 : 4 (rising edge) input
VCLK tclk(H) tclk(L) CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF VPA[7:0] Cb0 Cb1 Cb2 Cb3 ... Cbxxx Cbxxx
VPB[7:0]
Y0
Y1
Y2
Y3
...
Yxxx
Yxxx
VPC[7:0]
Cr0 th(D) tsu(D)
Cr1
Cr2
Cr3
...
Crxxx
Crxxx
001aai425
Fig 15. Timing YCbCr 4 : 4 : 4 (rising edge) input
VCLK tclk(H) CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF Cb0 th(D) tsu(D) tsu(D) Y0 Cr0 Y1 th(D)
001aai426
tclk(L)
VPB[7:0]; VPA[3:0]
...
Crxxx
Yxxx
Fig 16. Timing YCbCr 4 : 2 : 2 ITU656-like double edge (rising and falling) input
TDA9981B_1
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TDA9981B
150 MHz pixel rate HDMI transmitter
VCLK tclk(H) tclk(L) CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF Cb0 th(D) tsu(D)
001aai427
VPB[7:0]; VPA[3:0]
Y0
Cr0
Y1
...
Crxxx
Yxxx
Fig 17. Timing YCbCr 4 : 2 : 2 ITU656-like single edge external (rising edge) input
VCLK tclk(H) tclk(L) CONTROL INPUTS HSYNC/HREF VSYNC/VREF DE/FREF Y0 Y1 Y2 Y3 Y4 Y5 ... th(D)
VPB[7:0]; VPA[3:0]
VPC[7:0]; VPA[7:4]
Cb0
Cr0
Cb2 tsu(D)
Cr2
Cb4
Cr4
...
001aai428
Fig 18. Timing YCbCr 4 : 2 : 2 semi-planar external synchronization (rising edge) input
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TDA9981B
150 MHz pixel rate HDMI transmitter
14. Application information
DAC DENC G ADC DSP DAC
CVBS/Y/(G)
C/Pb/(B)
LO
audio I2S-bus or S/PDIF
AUX data
DAC
8
Pr/(R) HDMI data stream
HDMI TX
STEREO AUDIO DAC
001aai429
Fig 19. Application diagram for Set-Top Box
DAC DVD READ ENGINE DENC DSP DAC
CVBS/Y/(G)
C/Pb/(B)
audio I2S-bus or S/PDIF
DAC AUX data HDMI TX
8
Pr/(R)
HDMI data stream
STEREO AUDIO DAC
001aai430
Fig 20. Application diagram for DVD player
TDA9981B_1
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TDA9981B
150 MHz pixel rate HDMI transmitter
reset digital video (up to 24 bits) MICROPROCESSOR MASTER MPEG2 DECODER sync signals audio, S/PDIF and I2S-bus IRQ I2C-bus MASTER SLAVE I2C-bus MASTER HDMI
TMDS clock TMDS channel 0 TMDS channel 1 TMDS channel 2 hot plug detect DDC (SCL and SDA) SLAVE HDMI RECEIVER/ REPEATER
TDA9981B
HDMI SOURCE
E-EDID SLAVE ADDRESS A0 CEC line
001aai220
Fig 21. Transmitter connection with external world
TDA9981B_1
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TDA9981B
150 MHz pixel rate HDMI transmitter
15. Package outline
LQFP80: plastic low profile quad flat package; 80 leads; body 12 x 12 x 1.4 mm SOT315-1
c
y X A 60 61 41 40 Z E
e E HE wM bp pin 1 index 80 1 20 ZD bp D HD wM B vM B vM A 21 detail X Lp L A A2 A1 (A 3)
e
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.16 0.04 A2 1.5 1.3 A3 0.25 bp 0.27 0.13 c 0.18 0.12 D (1) 12.1 11.9 E (1) 12.1 11.9 e 0.5 HD HE L 1 Lp 0.75 0.30 v 0.2 w 0.15 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7o o 0
14.15 14.15 13.85 13.85
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT315-1 REFERENCES IEC 136E15 JEDEC MS-026 JEITA EUROPEAN PROJECTION
ISSUE DATE 00-01-19 03-02-25
Fig 22. Package outline SOT315-1 (LQFP80)
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150 MHz pixel rate HDMI transmitter
16. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
16.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
16.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
16.3 Wave soldering
Key characteristics in wave soldering are:
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities
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TDA9981B
150 MHz pixel rate HDMI transmitter
16.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 23) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 27 and 28
Table 27. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 28. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 23.
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150 MHz pixel rate HDMI transmitter
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 23. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
17. Soldering: additional information
The package of this device supports the reflow soldering process only.
18. Abbreviations
Table 29. Acronym AC-3 ADC AV CEC CMOS DAC DDC DENC DSP DTS DVD DVI EAV E-EDID HBM HDMI
TDA9981B_1
Abbreviations Description Active Coding-3 Analog-to-Digital Converter Audio Video Consumer Electronics Control Complementary Metal-Oxide Semiconductor Digital-to-Analog Converter Display Data Channel Digital video ENCoder Digital Signal Processor Digital Theater Systems Digital Versatile Disc Digital Visual Interface End of Active Video Enhanced Extended Display Identification Data Human Body Model High-Definition Multimedia Interface
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TDA9981B
150 MHz pixel rate HDMI transmitter
Abbreviations ...continued Description High-Definition Television Hot Plug Detect Interrupt ReQuest Local Oscillator Linear Pulse-Code Modulation Least Significant Bit Low-Voltage Transistor-Transistor Logic Most Significant Bit One-Time Programmable Phase Alternating Line Pulse-Code Modulation Phase-Locked Loop Personal Video Recorder Red, Green, Blue Start of Active Video Set-Top Box Sony/Philips Digital Interface Transition Minimized Differential Signaling Transmitter Extended Graphics Array color space used by the NTSC and PAL systems color space originally defined by the ITU-R BT.601
Table 29. Acronym HDTV HPD IRQ LO L-PCM LSB LV-TTL MSB OTP PAL PCM PLL PVR RGB SAV STB S/PDIF TMDS Tx XGA YUV YCbCr
19. Revision history
Table 30. Revision history Release date 20080704 Data sheet status Product data sheet Change notice Supersedes Document ID TDA9981B_1
TDA9981B_1
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150 MHz pixel rate HDMI transmitter
20. Legal information
20.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
20.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data -- The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.
20.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
20.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
21. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
TDA9981B_1
(c) NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 01 -- 4 July 2008
40 of 41
NXP Semiconductors
TDA9981B
150 MHz pixel rate HDMI transmitter
22. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5.1 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 8 8.1 System clock. . . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2 Video input processor . . . . . . . . . . . . . . . . . . . . 8 8.3 Synchronization . . . . . . . . . . . . . . . . . . . . . . . 18 8.3.1 Timing extraction generator . . . . . . . . . . . . . . 18 8.3.2 Data enable generator . . . . . . . . . . . . . . . . . . 18 8.4 Input and output video format . . . . . . . . . . . . . 18 8.5 Upsampler . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.6 Color space converter. . . . . . . . . . . . . . . . . . . 19 8.7 Downsampler . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.8 Audio input format. . . . . . . . . . . . . . . . . . . . . . 19 8.9 S/PDIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.10 I2S-bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.11 Power management . . . . . . . . . . . . . . . . . . . . 20 8.12 Interrupt controller . . . . . . . . . . . . . . . . . . . . . 20 8.13 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.14 HDMI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.14.1 Output HDMI buffers . . . . . . . . . . . . . . . . . . . . 21 8.14.2 Pixel repetition . . . . . . . . . . . . . . . . . . . . . . . . 21 8.14.3 HDMI and DVI receiver discrimination . . . . . . 21 8.14.4 DDC channel . . . . . . . . . . . . . . . . . . . . . . . . . 21 8.14.4.1 E-EDID reading. . . . . . . . . . . . . . . . . . . . . . . . 21 8.14.5 RxSense detection . . . . . . . . . . . . . . . . . . . . . 21 8.15 I2C-bus interface . . . . . . . . . . . . . . . . . . . . . . . 22 9 I2C-bus register definitions . . . . . . . . . . . . . . 22 9.1 I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . . 22 10 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 23 11 Thermal characteristics. . . . . . . . . . . . . . . . . . 23 12 Static characteristics. . . . . . . . . . . . . . . . . . . . 24 13 Dynamic characteristics . . . . . . . . . . . . . . . . . 26 13.1 Input format. . . . . . . . . . . . . . . . . . . . . . . . . . . 27 13.2 Example of supported video . . . . . . . . . . . . . . 28 13.3 Timing diagrams . . . . . . . . . . . . . . . . . . . . . . . 31 14 Application information. . . . . . . . . . . . . . . . . . 33 15 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 35 16 16.1 16.2 16.3 16.4 17 18 19 20 20.1 20.2 20.3 20.4 21 22 Soldering of SMD packages . . . . . . . . . . . . . . Introduction to soldering. . . . . . . . . . . . . . . . . Wave and reflow soldering . . . . . . . . . . . . . . . Wave soldering. . . . . . . . . . . . . . . . . . . . . . . . Reflow soldering. . . . . . . . . . . . . . . . . . . . . . . Soldering: additional information . . . . . . . . . Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 36 36 36 37 38 38 39 40 40 40 40 40 40 41
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2008.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 4 July 2008 Document identifier: TDA9981B_1

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